1. Field of the Invention
The present invention relates to a dynamic type semiconductor memory device (Dynamic Random Access Memory) wherein a memory cell is formed of a capacitor and a MOS transistor, and particularly to a DRAM wherein a memory cell is formed by use of semiconductor pillars, which are separated by groove and arrayed in a matrix manner, and its manufacturing method.
2. Description of the Related Art
A MOS type DRAM has been highly integrated by fining an element, and a capacity has been made large. As a DRAM structure, which is suitable for highly integrating the element and enlarging its capacity, there has been proposed a stacked cell structure in which a groove running horizontally and vertically in a semiconductor substrate and a plurality of semiconductor pillars are arrayed in a matrix manner, and a capacitor and a MOS transistor are vertically stacked on each semiconductor pillar (For example, see Published Unexamined japanese Application No. 60-152056.) According to this structure, a capacitor electrode (cell plate) is buried in the bottom of the groove, and a gate electrode is overlaid thereon so as to enclose the semiconductor pillar, thereby forming a memory cell. Since the capacitor and the MOS transistor are vertically stacked, an occupied area of the memory cell is small and the memory cell can be highly integrated.
However, in this structure, a groove having a depth of about 10 .mu.m must be formed and there is required a process in which a film is vertically buried in the groove by a CVD method and stacked. Moreover, impurity diffusion must be performed on the side surface of the semiconductor pillar in order to form a diffusion layer serving as a storage node. For these reasons, a manufacturing process is complicated. Furthermore, since a deep groove must be formed in the substrate, distortion is easily generated in the substrate. Due to distortion of the substrate, a memory holding characteristic is easily deteriorated and soft error resisting worsens.